And any innovation in synthesis has been very incremental over a long period of time with a lot of hardwork. More recently (past 10 years!) a push for physical synthesis which pushes the placement information back into the logic synthesis environment. Almost every major cad vendor has physical synthesis in the flow.

In the present day synthesis market, jargon and marketing claims wont just cut it and only benchmarks will prove which synthesis tool is better.

From a technical perspective, I think you are absolutely correct with your first concern where you say it is not really possible to close timing without considering the real, propagated clock tree.

You are also correct in pointing out that the other synthesis vendors do not optimize with the clock either.

The best technical solution for your concern is a combination of Oasys’ product and a clock concurrent optimization tool like Rubix: Oasys does a very fast synthesis and placement to get timing into the ballpark. Rubix then does a detailed physical optimization while building the clock trees at the same time. Rubix essentially builds a skewed clock network specifically tailored to match the logic while at the same time optimizing the logic to match the clock. This offers a fundamental solution to the problem you highlight. There is really no reason to view physical synthesis and CTS as two different steps. And you can forget about clock balancing – that has become an increasingly irrelevant holdover from the past.

Clock concurrent optimization closes design timing in propagated clock mode with full visibility of OCV derates, clock-gate timing, actual insertion delays, etc.

I’m glad that you recognized that clocks area major missing piece in traditional timing optimization approaches.

Good to hear from you after all these years. I should have posted something about synthesis sooner

Someone came up with a idea on Twitter that we really need to objectively benchmark the tools to see which one really performs the best. Just like with the BCS in college football, we really need a playoff to settle this thing on the field of play.

If such a benchmark could be arranged, and if it were fair, would Cadence participate?

Oasys and Synopsys: If you are reading this, would you participate?

Moment of truth.

Harry

1. My first comment has to do with getting to meaningful optimization almost immediately in the synthesis flow and for this I could not agree more. In the RTL-Compiler world, we have something called Physical Layout Estimators that are used to accurately estimate 80 – 90% of the wires in the design during the initial synthesis. We have found this to give the best results while leaving the estimation of the last 10-20% of wires to our RC-Spatial or RC-Physical technology. These technologies use real placement to estimate these outlying wires.
2. The RTL partitioning idea, while interesting, seems a bit impractical in today’s world of global design teams and IP reuse. It is very unlikely that any designer has the ability to let a tool repartition the design and move RTL from one layout block to another automatically. Most of these decisions are made based on the chip level architecture and data flow and are defined very early in a project.. I would also imagine that this would make any post-synthesis verification a nightmare at best, and impossible at worst. And trying to perform an automated ECO after this would most likely be impossible.
3. As for your comment on physical optimization after the initial synthesis, this is one place where RTL-Compiler really shines. Over the last few years we have developed significant advances in physical synthesis. Not only can we optimize based on legal placement, but we have also added the ability to modify the design in order to reduce congestion, improve timing, and reduce area and power, all based on detailed physical information. This technology also allows us to write out a full legal placement to feed forward to any P&R tool.

So, in conclusion, I would like to say to Oasys welcome to the Logic Synthesis world. It has always been the case that more awareness of the issues surrounding synthesis are good for the tools and good for our customers. We are confident that we have the absolute best synthesis on the market and with continued research and development will continue to do so for the foreseeable future. If you would like to discuss this further, please feel free to contact me at jflieder@cadence.com. If nothing else, it would be good to catch up, it’s been a long time.