Comments on: Verification Methodology Poll http://theasicguy.com/2009/02/03/verification-methodology-poll/ sharing insights into the people side of ASIC design Sat, 11 Feb 2012 20:13:29 +0000 http://wordpress.org/?v=2.3.2 By: harry http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-451 harry Sat, 07 Feb 2009 04:21:16 +0000 http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-451 Regarding SystemC/C/C++, I've had several comments that it should have been included in the poll. Most people have been putting it in "Other", but it probably deserves its own category. Regarding SystemC/C/C++, I’ve had several comments that it should have been included in the poll. Most people have been putting it in “Other”, but it probably deserves its own category.

]]> By: arunava http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-449 arunava Sat, 07 Feb 2009 03:01:43 +0000 http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-449 What i'm wondering is why there is no "systemC" and "C/C++"? What i’m wondering is why there is no “systemC” and “C/C++”?

]]> By: Jeremy Ralph http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-434 Jeremy Ralph Wed, 04 Feb 2009 17:12:20 +0000 http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-434 That is a pretty cool survey tool! I wonder how big the sample size needs to be for this survey to be statistically significant. Another variable that might be interesting is to know who is doing fixed (ASSP/ASIC) vs. programmable logic (FPGA) designs. My guess is that FPGA developers are more likely to use VHDL for verification. That is a pretty cool survey tool! I wonder how big the sample size needs to be for this survey to be statistically significant. Another variable that might be interesting is to know who is doing fixed (ASSP/ASIC) vs. programmable logic (FPGA) designs. My guess is that FPGA developers are more likely to use VHDL for verification.

]]> By: harry http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-431 harry Wed, 04 Feb 2009 07:05:45 +0000 http://theasicguy.com/2009/02/03/verification-methodology-poll/#comment-431 Day 1 - Feb 3, 2009 The survey is starting to pick up steam and generate some interesting data: 1) Early lead was for VMM, then OVM caught up, then e started to pipe up. I think there might have been some ballot stuffing going on, but I guess all's fair. 2) Have 30 respondents so far and only 2 (7%) are not planning to use some sort of System Verilog methodology; i.e. using Verilog or VHDL alone. 3) 26/30 (87%) using VMM or OVM, but only 3 (10%) of those are using both (likely consultants). 4) No AVM and only 4 using RVM/Vera. 9 (30%) using eRM/e. I'll be back tomorrow with some more analysis. Feel free to post a comment with your own interpretations. harry Day 1 - Feb 3, 2009

The survey is starting to pick up steam and generate some interesting data:

1) Early lead was for VMM, then OVM caught up, then e started to pipe up. I think there might have been some ballot stuffing going on, but I guess all’s fair.

2) Have 30 respondents so far and only 2 (7%) are not planning to use some sort of System Verilog methodology; i.e. using Verilog or VHDL alone.

3) 26/30 (87%) using VMM or OVM, but only 3 (10%) of those are using both (likely consultants).

4) No AVM and only 4 using RVM/Vera. 9 (30%) using eRM/e.

I’ll be back tomorrow with some more analysis. Feel free to post a comment with your own interpretations.

harry

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