Comments on: DVCon Survey Results - What Do They Mean? http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/ sharing insights into the people side of ASIC design Sat, 11 Feb 2012 20:37:23 +0000 http://wordpress.org/?v=2.3.2 By: Jim Lewis http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-435 Jim Lewis Wed, 04 Feb 2009 18:25:06 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-435 Harry, Not surprising results since at this point DVCon is irrelevant to people using a VHDL only verification methodology. The conference does not have any significant VHDL papers since the program committee rejects them, so how would someone justify attending? Cheers, Jim Harry,
Not surprising results since at this point DVCon is irrelevant to people using a VHDL only verification methodology. The conference does not have any significant VHDL papers since the program committee rejects them, so how would someone justify attending?

Cheers,
Jim

]]> By: harry http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-430 harry Tue, 03 Feb 2009 08:58:54 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-430 Jeremy et al, If you'd like to weigh in on the verification methodology question, you can vote (anonymously) at <a href="http://www.doodle.com/participation.html?pollId=u5ust5s73h8y9r62" rel="nofollow">the following link</a>. I'd love to see if we can get more respondents online than DVCon in person. That would be really cool. harry Jeremy et al,

If you’d like to weigh in on the verification methodology question, you can vote (anonymously) at the following link.

I’d love to see if we can get more respondents online than DVCon in person. That would be really cool.

harry

]]> By: Jeremy Ralph http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-425 Jeremy Ralph Sat, 31 Jan 2009 05:54:01 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-425 Seeing Verilog as a property specification language was a surprise to me too. I'm surprised there isn't more VHDL for design and I'm really surprised to see the SV is higher for design than VHDL. It's encouraging to see the SV numbers, but that may be because this is a Verification conference. I'd be interested to know what proportion of the SV is OVM vs. VMM. Seeing Verilog as a property specification language was a surprise to me too. I’m surprised there isn’t more VHDL for design and I’m really surprised to see the SV is higher for design than VHDL. It’s encouraging to see the SV numbers, but that may be because this is a Verification conference. I’d be interested to know what proportion of the SV is OVM vs. VMM.

]]> By: harry http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-419 harry Wed, 28 Jan 2009 04:12:46 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-419 The % of e and Vera users looks REALLY low. <a href="http://www.deepchip.com/items/dvcon07-08.html" rel="nofollow">John Cooley's 2007 DVCon numbers</a> had over 40% using e or Vera. Same conference .... same attendees. What gives? The % of e and Vera users looks REALLY low. John Cooley’s 2007 DVCon numbers had over 40% using e or Vera. Same conference …. same attendees.

What gives?

]]> By: JohnB http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-418 JohnB Wed, 28 Jan 2009 03:05:25 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-418 Interesting data. Thanks for sharing. Maybe using "Verilog" in #4 means using native Verilog assertions? "This shouldn't happen, if it does, issue a message or corrupt the data." Not quite what I'd formally call a property, but it is an assertion. Interesting data. Thanks for sharing.

Maybe using “Verilog” in #4 means using native Verilog assertions? “This shouldn’t happen, if it does, issue a message or corrupt the data.” Not quite what I’d formally call a property, but it is an assertion.

]]> By: harry the ASIC guy http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-417 harry the ASIC guy Wed, 28 Jan 2009 00:49:45 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-417 Brad, I was wondering that myself. Only thing I could think was that people confused SVA and Verilog. Perhaps the same for VHDL? Come to think of it, I would have expected some % of people using no assertions at all. Harry Brad,

I was wondering that myself. Only thing I could think was that people confused SVA and Verilog. Perhaps the same for VHDL?

Come to think of it, I would have expected some % of people using no assertions at all.

Harry

]]> By: Brad Pierce http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-416 Brad Pierce Wed, 28 Jan 2009 00:25:37 +0000 http://theasicguy.com/2009/01/27/dvcon-survey-results-what-do-they-mean/#comment-416 How could "Verilog" be the answer to question 4? -- "Which primary property specification (assertion-based verification) language do you use?" How could “Verilog” be the answer to question 4? — “Which primary property specification (assertion-based verification) language do you use?”

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